The present invention relates generally to memory systems, and more particularly, to methods and systems for using and testing the integrity of memory systems.
Solid state memory systems are manufactured in great volume and in many different forms including volatile type memory circuits and non-volatile type memory circuits. As part of the production process the completed memory circuits are tested to confirm the proper operation of the memory. Specifically, the completed memory circuits are tested to confirm the memory circuit can be written to and the data that was written (i.e., stored) in the memory circuit can accurately be read back from the memory circuit. Typically, a high voltage write and erase cycles and read operations are applied to the memory circuit. The higher voltage of the operations physically stress the semiconductor devices (e.g., gates, P-N junctions, conductive lines, etc.) greater than typical operating voltage so as to cause physically weaker semiconductor devices to fail.
There are many types of tests performed as part of the manufacturing process. These manufacturing process tests can reliably only identify memory circuits that fail due to manufacturing defects or fail during early operations, often referred to as infant mortality, occurring in an early portion of the projected service life of the memory circuit.
The memory circuits that pass the manufacturing process tests are then shipped to end users and distributors. Unfortunately, many memory circuits can fail later in the projected service life, well after the memory circuits successfully passed the manufacturing process tests. When memory circuits fail, the data stored therein can be lost, corrupted or otherwise rendered not accessible and effectively lost.
In view of the foregoing, there is a need for system and method for preventing data loss due to memory cell failure.